Abstract

 

Day 1         9/11/2015
9:00-9:30

Mr. Dudi Tash, SI\PI Expert, Dgtronix

Lecture: Nonhomogeneous Current Distribution In Power Vias

 

PDN design for High Power Consuming SoCs and FPGAs require careful Power Vias design. This session will focus on nonhomogeneous current distribution through Power Vias and suggested guidelines based on a test case on 1V/100A Virtex Ultrascale XCVU440 FPGA core voltage design. 

9:30-10:30

Dr. Eric Bogatin, Signal Integrity Evangelist, Teledyne LeCroy

Lecture: Reducing Losses In Differential Channels

 

The PDN includes all the structures from the VRM to the pads on the IC. Its purpose is to provide low noise DC voltage to power all the active devices for both core and I/O. How we do this, and how we know if the design will work will be covered in this series of three 50 minute workshops.

The starting place for PDN design is the impedance profile in the frequency domain. We will show that most of PDN problems can be identified and fixed by looking in the frequency domain with simulation and measurement examples. Just a few figures of merit describe everything we need to know about behavior of the PDN which can be related to simple parallel resonant circuits.

With this perspective, we’ll look at the root cause of most PDN problems, and the features in the PDN system, including the on-die capacitance, package lead inductance, VRM and all the decoupling capacitors. From the analysis of the root cause of the problem, the solution will be obvious.

We’ll explore a number of the popular solutions offered for PDN design, such as the big V and multiple V approaches and show that much of what is suggested in the popular press is wrong, and how to do the analysis correctly. Equally important, we’ll look at the real reasons most PDN systems “work” even when many of the decoupling capacitors are removed from the circuit board. This will suggest some of the challenges in testing a robust design.

 

Session 1: A Crash Course In Power Integrity Principles

 

- Inductance

- Parallel resonance circuits, peaks, characteristic impedance and damping

- Impedance profiles: measured and simulated

- Switching noise, current and impedance

- Cavity impedance

10:45-11:45
11:45-13:00

Session 2: The real problem in PDN Design, the Bandini Mountain 

 

- ODC and package lead inductance

- Features and characteristics

- Step response to transient current loads

- Typical values

- Why some products work just fine sometimes

 

Session 3: The most important design solutions for a robust PDN

 

- Typical PDN architectures

- What to do to impact the Bandini Mountain

- Why most of what you see in the popular press is wrong

- The only way of affecting the Bandini Mountain at the board level

- The three most important design issues with decoupling capacitors 

14:00-14:45

Mr. Mike Resso, Signal Integrity Application Scientist, Keysight Technologies

Lecture: A New Calibration Method For Characterization Of PCB insertion Loss

 

There are several existing techniques like Direct Loss Subtraction, Through-Reflection-Line (TRL) calibration and Automatic Fixture Removal (AFR) with 2XThrough fixtures for characterizing PCB unit length insertion loss. In this paper, a new method for characterizing PCB loss by using AFR with 1X Open fixtures is proposed. This new method has been proved to have the similar accuracy with TRL and AFR with 2X throughs, but can save much more PCB area and measurement time. Based on measurements of transmission lines with different reference impedance, the measurement bandwidth, accuracy, efficiency and cost of these techniques are compared.

14:45-15:30
Dr. Davi Correia, Signal Integrity Engineer, Molex Incorporated

Lecture: High-Speed Systems: What Makes or Breaks A 25Gbps Channel

 

When designing a backplane channel, system engineers are faced with a multitude of options. Connectors, board materials, board layout and chip characteristics are some of the variables that will impact the performance of his system. How relevant each component is to the overall quality of the system is usually open to debate. Should the engineer invest on a premium connector? Will that have a significant impact if backdrilling is not used? If the board material is not the best possible, will he need a very powerful chip? Could he use a mid-range connector if he uses a premium board? To answer those and some other questions that the system engineers face on a daily base, we will create a set of channels by combining different connector types, different board materials, backdrilling and no backdrilling and different chip settings. Different channel lengths (short and long) will be considered. Each channel will be evaluated operating at 25Gbps with IEEE.802.3bj channel operating margin (COM). That way, we will be able to identify the key components when designing a backplane channel.

15:45-16:45

Mr. Dror Haviv, Signal/Power Integrity and Electromagnetism Specialist, Rafael

Lecture: The Impact Of Conductors' Power Dissipation On The PCB's Temperature Rise 

 

With the advancement of technology, the electronic cards are becoming more complex and increasingly dense. This is reflected by large number of components, multiple voltage levels, high power conductors routing, small layout areas, layout constrains and operation at high ambient temperatures. As a result, in many cases, the temperature of the electronic card might rise considerably due to significant power dissipation of the power supply conductors and thereby to cause damage to components and/or to the PCB itself.

The lecture, which is a part of research work, will focus on the impact of power supply conductors' heating as a supplement to the traditional PCB's thermal design considerations. Additionally, the lecture will detail on power supply conductors' design considerations, heat transfer mechanisms in PCBs, relevant standards, measurement and simulation results of different types of PCB conductors' heating.

16:45-17:15
Mr. Shai Sayfan-Altman, Application Engineer, ANSYS

Lecture: Common-Mode Noise Suppression Using Metamaterials

 

As data rate is getting higher the use of differential signals has become essential in digital design, this is thanks to the low electromagnetic interference, high immunity to noise and crosstalk. However due to skew between the differential signals as a result of layout or drivers common-mode noise is introduced to the system and the common-mode rejection ratio of the device could be violated.

A technique based on metamaterials for mitigating common-mode noise when using differential signals is introduced. This is done by using a miniaturized common-mode suppression planar filter, which may be effectively presented as a transmission line with a negative permittivity substrate.

Day 2        10/11/2015
9:15-10:00
Dr. Avri Frenkel, Representative and Tech Support of CST in Israel, Anafa Electromagnetic Solutions Ltd.

Lecture: On Radiation Emissions From High-Speed PCBs

 

The presentation will cover the origin of Radiation Emissions from both signal lines and power planes, layout rules related to Radiation Emissions, efficient 3D simulation  flows to simulate Radiation Emissions from high-speed PCBs, and comparisons to measurements.

10:00-11:00

Mr. Cristian Filip, Product Marketing Manager High Speed Analysis Products SDD, Mentor Graphics Corp.
Lecture: Incorporating COM Into An SI Analysis Methodology

 

To satiate the demand for higher speeds, SerDes is breaking the 25+ GBps bandwidth.  These speeds bring along with it new challenges, and not purely technical ones.  As always, any new technology needs to be a breakthrough not just in terms of physics, but also in terms of market economics.

At such high speeds, the demand is to be able to design products which are not just reliable in production, but also easy to design.  This balance has yielded new parametrics such as Channel Operating Margin (COM), Insertion Loss to Crosstalk Ration (ICR) and Integrated Crosstalk Noise (ICN) which help designers quickly asses the viability of a given channel. These parameters augment the traditional parameters of time domain analysis such as eye-masks and frequency domain analysis such as insertion or return loss masks.  These new parameters bridge the requirements of the complexities of very high speed validation with a variety of interconnects on one hand, and practically simple calculations on the other.

This presentation will highlight the new parameters - focusing on COM, and how it is used to validate very high speed signals as well as the practical advantages of using them over traditional methods.  There is also a highlight on how well COM correlates important measures such as BER with the traditional methods of calculating them.  The presentation will also highlight the effects of various common design tradeoffs on COM by means of 3D simulations (and measurements).

11:15-13:00
Mr. Jeff Loyer, Signal and Power Integrity Product Manager, Altium 
Lecture: PCB Material and Copper Foil Considerations for Signal Integrity 

 

Part 1- This presentation is intended to enable signal integrity engineers to specify stackup requirements to meet their performance requirements at the lowest cost.  It reflects many key learnings gleaned while leading Intel's "PCB Electrical Performance Work Group", chartered with ensuring advanced signal integrity needs can be met in low cost, high volume manufacturing environments. It provides understandable but accurate representations of the fundamental physics of insertion loss, explains the consequences of actual PCB manufacturing tradeoffs on loss and crosstalk, and provides concrete examples of various builds vs. performance.

14:00-14:45
Mr. Jeff Loyer, Signal and Power Integrity Product Manager, Altium
Lecture: PCB Material and Copper Foil Considerations for Signal Integrity 

 

Part 2.

14:45-15:30
Mr. Alex Manukovsky, Technical Lead, Signal & Power Integrity Team, Networking Division, Intel

Lecture: Robust Deembedding Techniques- Practical Solutions To Lab Correlation Challenges

 

Eliminating channel effect (or Deembedding) is a well-studied topic, faced by SI engineers in our everyday work. While traditional techniques work well on paper, in the lab in real life, they often fail to provide meaningful results, due to differences between the model and the actual channel. This presentation will guide on how to deembed a segment of a channel in real life and still achieve a correlation to lab measurements. It will cover a common case, when the actual channels parameters deviate from the model used for Deembedding.
The work deembedding technique introduced works well in this scenario, and provides accurate results, relying only on channel properties: Passivity, Causality, and Reciprocity.

15:45-16:15
Mr. Eli Recht, Chief Engineer, EMC Department, ELOP/Elbit
Lecture: EMC & SI In Electro Optic Defense And Commercial Systems

 

- Introduction to electro optic systems

- Comparison between defence and commercial systems

- Design rules of EMCand SI in defense and commercial systems.

- Simple and quick analysis of EMC radiated emission and radiated immunity.

- EMC standards and regulations.

16:15-16:45

Mr. Liav Ben-Artsi, Senior Signal Integrity Manager, Marvell Israel

Lecture: Testing 25Gbps for 802.3bj 

 

Testing Rx interference tolerance test In the IEEE 100Gbps over four lanes standard for backplanes and cables introduces some new concepts, such as using COM and the possibility to use a “golden device”

This lecture will discuss these new concepts in conducting Rx testing.

16:45-17:15
Mr. John Calvin, Ultra Performance Instrument Planner/DataCom Segment Manager, Tektronix.
Lecture: 100G and 400G Optical Ethernet and general Datacom testing requirements

 

100G Networks ranging from long range 100GBASE-LR4 to short reach 100GBASE-SR4 systems have unique testing requirements.  Emerging 400GBASE-LR8 is starting to coalesce and is already driving T&M directions with its unique needs.   This course will focus on R&D for Optical LAN and Electrical and Optical interconnects at highest speeds. 

Day 3       +11/11/2015
9:30-13:00
Dr. Eric Bogatin, Signal Integrity Evangelist, Teledyne LeCroy
Lecture: S-parameter boot camp

 

Session 1: 

 

- What are S-parameters
- Where do they come from
- Viewing Touchstone files in the frequency and time domains with a free tool
- The most important features of return and insertion loss

 

Session 2:

 

- Ripples in return and insertion loss
- Dips in insertion loss
- Differential S-parameters
- Converting from SE to diff S-parameters

 

Session 3:

 

- SDD21 and attenuation
- SDD21 and eye diagrams
- Building channel models form S-parameter elements
- SDD11 and TDR of a channel

 

Lecture: High speed serial link boot camp

 

Session 1: 

 

- The four problems with channels

- Engineering losses

- Differential pairs and tight or loose coupling

- Cross talk and differential pairs

 

Session 2:

 

- Engineering discontinuities

- Designing transparent vias

- How long a stub is too long

- Channel models and eye diagram

 

Session 3:

 

- What is jitter and the time interval error

- Jitter from ISI and the PDN

- Random jitter

- Equalization and opening eyes

Initiated By:

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