Agenda

*The Agenda may be subject to changes
DAY
#1
MAY 26, 2019 
 
8:00-9:00

Registration and Breakfast

Sign in, make yourself a cup of coffee, and meet your fellow engineers.

9:00-10:30

Measurement-Based, Harmonic Balance VRM Model

Steve Sandler, Managing Director, Picotest

About the Speaker  

10:30-10:45
Break
10:45-12:15

Power Related Noise in Distributed Systems

Steve Sandler, Managing Director, Picotest

About the Speaker 

12:15-13:15
Lunch
13:15-14:45

The Return Loss (RL) evolution - Effective Return Loss (ERL) to substitute RL

Liav Ben-ArtsiStaff Signal Integrity Manager, Marvell

About the speaker | 

14:45-15:00
Break
15:00-16:00

Distributed Decoupling Capacitors Application for PDN Designs of Fine Pitch BGA Products (Presented at DesignCon2019)

Alex Manukovsky, Technical lead of the Signal & Power Integrity, Intel &

Shimon Mordooch, R&D Project Manager, Harmonic Video Networks

About Alex manukovsky

MAY 27, 2019 
DAY
1
DAY
#2
 
8:00-9:00

Registration and Breakfast

Sign in, make yourself a cup of coffee, and meet your fellow engineers.

9:00-10:30

Typical Cavity Resonators in PCBs and their Impact on

Signal and Power Integrity

Dror Haviv, Signal/Power Integrity and Electromagnetism Specialist, Rafael

About the Speaker 

10:30-10:45
Break
10:45-12:15
12:15-13:15
Lunch
13:15-14:15
14:15-14:30
Break
14:30-15:30
15:30-15:45
Break
15:45-16:45
*The schedule may be subject to changes