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*Subject to Changes

Alex Manukovsky



A step by step Guide for channel modeling and simulation that correlate to lab measurement for 25Gb NRZ and 56Gb PAM4 applications.

Alex Manukovsky

Alex Manukovsky is a Technical lead, of the Signal & Power Integrity team at Intel Networking Division, responsible for the development of indoor link simulator for high speed serial links, combining both traditional methods of frequency and time domain simulation along with AI machine learning capabilities. Alex focuses on simulation to lab correlation for high speed serial links for PCIe and Ethernet technologies and AI. His past work focused on channel modeling, robust deembedding and calibration techniques for VNA and TDR. His experience includes developing test equipment for compliance testing of serial I/O’s as well as lab measurement methodologies for volume testing and Si/Pi simulations. Alex joined Intel in 2010 after receiving his BSc in Electrical Engineering from the Technion – Israel Institute of Technology. He is currently pursuing his Master’s degree in System Engineering from the Technion – Israel Institute of Technology.

Amiram Jibly

Amiram Jibly



A step by step Guide for channel modeling and simulation that correlate to lab measurement for 25Gb NRZ and 56Gb PAM4 applications.

Amiram Jibly is a System Design Technical lead at the Network ASIC group at Intel, has been with Intel in the last 7 years and is experienced in package and board design for high speed systems.

His current work focuses on passive interconnect simulation for 56G interfaces as well as design for 25G and 56G electrical validation systems.

Terence Regan


Enabling 56 Gbps Solutions in Printed Circuit Board Technology

Terence Regan is a Field Applications Engineer at Amphenol Printed Circuits (APC), a leader in high technology, high speed, high reliability products for the military and commercial markets. Terence has been in the Printed Circuit Board industry for over 35 years.  His experience includes Military, Aerospace and High Reliability Commercial products.  He has supported leading-edge designs from concept through fabrication and assembly, including rigid, rigid-flex and RF/microwave technologies. With the direct support of OEM engineers and designers, he has guided cost effective material selection, design requirements including impedance control and fabrication improvements, to ultimately produce high yielding products for customers.  Terence holds a Bachelor of Science in Industrial Technology from San Jose State University.

Christine Marvell Harrington

Danilo Di Febo PhD

Modeling, design and optimization of electronic package

Danilo Di Febo was born in Atri (TE), Italy, in 1980. He received the Laurea degree in electronic engineering in 2009 and the Ph.D. degree in electrical and information engineering in 2013, both from the University of L’Aquila, L’Aquila, Italy.

The main focus of his activities was modeling and analysis of complex system, signal and power integrity on PCB, signal and power integrity on complex system that involve board placed in the final position, cables and all the connections, EMC analysis of integrated system.

In the past he worked on IBIS files, improving  their function and correct all the errors generated by IBIS rules checker, using a standalone tolls developed in Java, on EMC on satellite modules and avionic equipment’s,  and on FSV feature selective validation, a tool that implement an IEEE strategy to compare data using an engineering approach.

Currently he is working as application engineer at CST.

PCB Trace and Via Temperatures; How To Deal With Real World Variables

Douglas Brooks has a BS/EE and an MS/EE from Stanford and a PhD from the University of Washington. He has spent most of his career in electronic manufacturing industries, rising through the ranks to General Manager and President of his own firm. For the last 20 years he has owned a small engineering service firm and written numerous technical articles on Printed Circuit Board Design and Signal Integrity issues. He has published two books on these topics (Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall, 2003 and PCB Currents; How They Flow, How They React, Prentice Hall, 2013). He has also given seminars on PCB signal integrity several times a year  across the US, as well as Moscow, China, Taiwan, Japan, and Canada.


Most recently, Brooks has collaborated with Dr. Johannes Adam (Adam Research, Leiman, Germany) on PCB current/temperature relationships. The collaboration has resulted in numerous articles and a book, PCB Trace and Via Currents and Temperatures: The Complete Analysis (available through, 2016). His primary focus in all of these efforts has been making complex technical issues easily understood by those without advanced degrees.


Brooks is now retired and lives in Seattle, WA., with his wife of 49 years. They have three children and 7 grandchildren.

Doug Brooks
Heidi Barnes

Power Integrity Ecosystem 

Heidi is working for Keysight EEsof EDA in the application of electromagnetic, transient, and channel simulators to solve the challenges of high speed SERDES and parallel bus communication links. Past experience includes 6 years in signal integrity for ATE test fixtures for Verigy, an Advantest Group, 6 years in RF/Microwave microcircuit packaging for Agilent Technologies, and 10 years with NASA in the aerospace industry.

James L. Drewniiak

Power integrity for printed circuit board design

James L. Drewniak is a Curator’s Professor of Electrical and Computer Engineering at Missouri S&T, and with the Electromagnetic Compatibility Laboratory.  He received B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign.    His research is in electromagnetic compatibility, signal and power integrity, and electronic packaging.  He leads a university research laboratory of 65 people that is internationally recognized for research in EMC and signal and power integrity, with funding that has included government and industry sources.  A key research funding component is the NSF Industry/University Cooperative Research Center (I/UCRC) for Electromagnetic Compatibility that is a consortium of approximately 20 companies, with over 20 funded projects.  He is a Fellow of the IEEE, 2013 recipient of the IEEE EMC Society’s Richard R. Stoddart Award, and a past Associate Editor of the IEEE Transactions on EMC.

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Kenneth Wyatt

Kenneth Wyatt is a Sr. EMC Engineer and President with EMC consulting company, Wyatt Technical Services LLC, and holds degrees in biology and electronic engineering.  He worked as a product development engineer for 10 years for various aerospace firms on projects ranging from DC-to-DC power converters, to RF and microwave systems for shipboard and space platforms. For over 20 years, he worked as a senior EMC engineer for Hewlett-Packard and Agilent Technologies in Colorado Springs where he provided comprehensive EMC design and troubleshooting services. During that time, he managed the product compliance and environmental test lab and provided advanced EMC training and corporate leadership for EMC.

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Radiated Emissions: Design Basics, Troubleshooting, and Precompliance Testing

Mike Resso

Mike Resso

Time & Frequency Domain Simulation-to-Measurement Techniques for Characterizing a USB Type-C Reference Channel

Mike Resso is the Signal Integrity Application Scientist in the Component Test Division of Keysight Technologies and has over twenty-five years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications.  His most recent activity has focused on the complete multiport characterization of high speed digital interconnects using Time Domain Reflectometry and Vector Network Analysis.  He has authored over 30 professional publications including a book on signal integrity. Mike has been awarded one US patent and has twice received the Agilent “Spark of Insight” Award for his contribution to the company. He received a Bachelor of Science degree in Electrical and Computer Engineering from University of California.

Nitin Bhagwath

SI Analysis of DDR Bus during Read/Write operation transitions

Nitin Bhagwath is a Technical Marketing Engineer at Mentor Graphics. He has designed
and architected high-speed systems for Hewlett Packard and Cisco for ten years. He has
been with the high-speed simulation group at Mentor Graphics for four years, where he
advises simulation design on multi-gigabit SerDes signals, power integrity and DDR
memory. Nitin represents Mentor Graphics at the JEDEC memory groups. Nitin has a
bachelors in Electronic Engineering from Bangalore University, an MS in EE from
Purdue University and an MBA from the Indian Institute of Management, Bangalore. 


Pavel Zivny

Optical signal characterization in PAM4 links

Pavel Zivny is a communications measurements domain expert with the high performance oscilloscopes group of Tektronix. One of his interests is the jitter/noise decomposition.  He was lucky to be able to contribute to both Tektronix jitter/noise toolbox and also the measurements in the IEEE 802.3 standard. 

Pavel was granted a number of oscilloscope related patents, authored industry articles, papers and represents Tektronix to high-speed serial data standards committees. Most of his papers are presented at DesignCon and for example, in 2016, a paper wrriten by Pavel and his colleagues was awarded a “Best Paper Award” – the title of the paper was , “Jitter, Noise Analysis and BER Synthesis on PAM4 Signals on 400 Gbps Communication Links”.

Pavel Zivny
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